The present invention generally relates to a semiconductor device and a method for fabricating the same, and more particularly relates to a power MOSFET with a reduced ON-state resistance but with an increased drain-source breakdown voltage and to a method for fabricating the same.
First, a conventional semiconductor device with a structure for increasing a drain-source breakdown voltage will be described with reference to FIG. 8. This semiconductor device is described in Japanese Laid-Open Publication No. 4-107877, which was filed by Matsushita Electronics Corporation.
This device includes: an n-type source region 107 and an n-type extended drain region 103, which are both formed within a p-type single crystalline silicon substrate 104; and a p-type buried region 102 enclosed in the n-type extended drain region 103. In part of the n-type extended drain region 103, a drain contact region 114 is provided to be in electrically contact with a drain electrode 110. The n-type source region 107, as well as a substrate contact region 108 formed within the surface of the p-type single crystalline substrate 104, is in electrically contact with a source electrode 111. And an anti-punchthrough region 109 is provided to surround the source region 107 and the substrate contact region 108.
A region between the source region 107 and the extended drain region 103 functions as a channel region. A gate electrode 106 is provided over the surface of the p-type silicon substrate 104 with a gate insulating film interposed therebetween. And the surface of the substrate 104 is covered with a thermal oxide film 105.
This semiconductor device is characterized by including: the n-type extended drain region 103, which is formed by a diffusion process within the p-type substrate 104 to have a relatively low dopant concentration; and the p-type buried region 102 formed inside the n-type extended drain region 103.
FIG. 9 illustrates the distributions of dopant concentrations and the distribution of a carrier concentration in the depth direction, which are both measured along the line X-Xxe2x80x2 in FIG. 8. In general, the conductivity type of a particular semiconductor region is determined as p- or n-type depending on the result of comparison in concentration between p- and n-type dopants existing in the particular semiconductor region. That is to say, if the concentration of the p-type dopant is higher in that region than that of the n-type dopant, then the conductivity type of the semiconductor region is p-type, and vice versa. It should be noted that the higher the concentration of an n-type dopant, the lower the ON-state resistance of a MOSFET.
Next, the ON- and OFF-state operations of this semiconductor device will be described.
The p-type buried region 102 is reverse-biased relative to the extended drain region 103. Accordingly, while this MOSFET is in its OFF state, a depletion layer expands not only from a pn junction between the p-type buried region 102 and the n-type extended drain region 103, but also from a pn junction between the p-type substrate 104 and the n-type extended drain region 103. By utilizing these depletion layers, the breakdown voltage of this MOSFET can be increased.
On the other hand, while the MOSFET is in its ON state, electrons are moving through the extended drain region. More specifically, the electrons are moving through part of the extended drain region 103 near the surface of the substrate 104, where the concentration of the n-type dopant is the highest, and through another part of the extended drain region 103 under the p-type buried region 102. However, if the p-type buried region 102 has been formed by an ordinary diffusion process, then the conductivity type of the surface region of the substrate 104, where the concentration of the n-type dopant is usually the highest, is inverted into p-type. As a result, the concentration of n-type carriers decreases and the ON-state resistance increases in that region. Thus, this structure can decrease the ON-state resistance of the MOSFET with the breakdown voltage thereof increased.
The method disclosed in Japanese Laid-Open Publication No. 4-107877 includes the steps of: forming the extended drain region 103 by implanting dopant ions into the p-type substrate 104 and diffusing the dopant through the substrate 104; implanting boron ions into the extended drain region 103 and then conducting a heat treatment; and thermally oxidizing the surface of the substrate 104. As a result of the final thermal oxidation process step, the concentration of the p-type dopant in the region between the p-type buried region 102 and the surface of the substrate 104 decreases, thus inverting the conductivity type of that region into n-type. During this thermal oxidation process step, the boron ions, existing in the region above the p-type buried region 102, are introduced into the silicon dioxide film 105 by utilizing the difference in coefficient of segregation between silicon and silicon dioxide. As a result of this thermal oxidation, the p-type buried region 102 is located at a distance from the surface of the substrate with the thin n-type region interposed therebetween. That is to say, the p-type buried region 102 is embedded in the extended drain region 103 so to speak. However, in order to invert the conductivity type of the region above the p-type buried region 102 into n-type by decreasing the concentration of boron in that region, a thermal oxide film with a relatively large thickness (e.g., 1 xcexcm or more) should be formed thereon.
In this conventional method, the depth of the p-type buried region 102 from the surface of the substrate and the control over the carrier concentration in the region between the p-type buried region 102 and the surface of the substrate are both dependent on the conditions under which the thermal oxide film 105 is formed. Accordingly, the carrier concentration in that surface region of the extended drain region 103 is affected by a variation in process parameters, including temperature and flow rate of oxygen gas, during the process step of forming the thermal oxide film 105. More specifically, the surface carrier concentration in the extended drain region 103 is very sensitive to, or greatly variable with, a rate at which the thermal oxide film 105 is formed and with the final thickness of the thermal oxide film 105. Accordingly, it is extremely difficult to precisely control the surface carrier concentration of the extended drain region 103 during the thermal oxidation process step.
As shown in FIG. 9, in the surface region of the semiconductor substrate, the concentration of the p-type carriers is only slightly different from that of the n-type carriers. The difference is so small that this delicate concentration balance is easily disturbed by various factors during the fabrication process. For example, if the concentration of the p-type carriers does not sufficiently decrease in that surface region during the formation of the p-type buried region 102, then the conductivity type at the surface of the p-type diffusion layer might be not completely inverted into n-type. Or even if the conductivity type has been successfully inverted into n-type, the concentration of the p-type carriers in the surface region may be greatly variable every time the p-type buried region 102 is formed. Such inconsistent inversion or greatly variable concentration is likely to broaden the variation range of the ON-state resistance (e.g., 1.2 to 2.0 xcexa9 per unit area) depending on the current passing through the extended drain region between the gate and drain electrodes, or considerably varies the characteristics of the device.
To reduce this variation, a method shown in FIGS. 10A and 10B may be employed. In the illustrated method, an extended drain region 26 is first formed within a p-type substrate 27, and then boron ions are implanted into the substrate 27 with a relatively high implant energy of 1 to 2 MeV. Specifically, according to this method, a thick resist film 24 with a relatively large thickness of about 3 to about 4 xcexcm is applied onto the surface of the p-type substrate 27 and then exposed to radiation and developed by photolithography to form an opening in the resist film 24. Thereafter, boron ions are implanted with high energy into the substrate 27 through this opening so as to reach a depth of about 1 xcexcm as measured from the surface of the extended drain region 26. As a result, a p-type buried region 28 is formed as shown in FIG. 10B. In accordance with this method, the uniformity of surface concentration in the extended drain region 26 is dependent on how the extended drain region 26 itself is formed. Thus, unlike the prior art described above, the process step of inverting the conductivity type of the p-type surface region into n-type by introducing boron ions into the oxide film 105 is no longer necessary. Consequently, the variation in ON-state resistance of the MOSFET can be reduced.
In order to form the p-type buried region 28 by such high-energy ion implantation, a patterned ion implantation mask such as resist film, metal film or insulating film should be formed on the substrate. Also, each edge of the patterned ion implantation mask is not completely parallel to the direction in which the ions are implanted. Accordingly, in the surface region of the substrate below the edge of the ion implantation mask, the profile of the dopant, which has been implanted into the substrate by the high-energy implantation technique, shifts toward the surface of the substrate. Also, to ensure sufficient blocking effect by the use of the ion implantation mask, the higher the implant energy is, the thicker the mask such as a resist film should be. In addition, to maintain a certain degree of vacuum within an ion implanter, the solvent, water and the like contained in a resist film should be vaporized by heating the semiconductor substrate in advance. However, if the resist film is thick, then the substrate should be heated for a longer time or at a higher temperature than usual. Nevertheless, if the substrate is heated under such a condition, then the edge of the thick resist film 24 is likely to incline and the resist film 24 is likely to have a trapezoidal cross section as shown in FIG. 10B. This is because the deformation of the thick resist film 24 usually results from the shrinkage of part of the resist film 24 that is not in contact with the substrate 27 rather than the other part of the resist film 24 in contact with the substrate 27. If the ions are implanted using such a deformed resist film 24 as a mask, then the thinned part of the resist film 24 at the edge thereof cannot perform the expected masking effect, or cannot sufficiently block the impinging ions. As a result, the dopant ions pass through that part of the resist film 24 to be implanted into a region of the substrate near the surface thereof as shown in FIG. 10B. That is to say, the outer periphery of the buried region 28 protrudes upward, i.e., toward the surface of the substrate, thereby forming a p-type region reaching the surface of the substrate. Such a p-type region, reaching the surface of the substrate, is formed to cross the path of a drain current between the gate region and the drain electrode, thus increasing the ON-state resistance of the device.
An object of the present invention is providing a semiconductor device with an increased- drain-source breakdown voltage and yet with a reduced ON-state resistance.
A semiconductor device according to the present invention includes: a semiconductor layer of a first conductivity type; a source region of a second conductivity type, the source region being formed within the semiconductor layer; a drain region of the second conductivity type, the drain region being formed within the semiconductor layer; a channel region provided between the source and drain regions; and a gate electrode formed over the channel region. The device further includes: a buried region of the first conductivity type, at least part of the buried region being included in the drain region; and a heavily doped region of the second conductivity type. The heavily doped region is provided at least between a surface of the semiconductor layer and the buried region. The concentration of a dopant of the second conductivity type in the heavily doped region is higher than that of the dopant of the second conductivity type in the drain region.
A method according to the present invention is a method for fabricating a semiconductor device including: a semiconductor layer of a first conductivity type; a source region of a second conductivity type, the source region being formed within the semiconductor layer; a drain region of the second conductivity type, the drain region being formed within the semiconductor layer; a channel region provided between the source and drain regions; a gate electrode formed over the channel region; and a buried region of the first conductivity type, at least part of the buried region being included in the drain region. The method includes the steps of: doping the semiconductor layer with a dopant of the second conductivity type for the drain region; doping the semiconductor layer with a dopant of the first conductivity type for the buried region; and forming a heavily doped region of the second conductivity type at least between the surface of the semiconductor layer and the buried region by further doping the semiconductor layer with the dopant of the second conductivity type.
Another semiconductor device according to the present invention includes: a semiconductor layer of a first conductivity type; a source region of a second conductivity type, the source region being formed within the semiconductor layer; a drain region of the second conductivity type, the drain region being formed within the semiconductor layer; a channel region provided between the source and drain regions; and a gate electrode formed over the channel region. The device further includes a buried region of the first conductivity type. At least part of the buried region is included in the drain region. The buried region is divided into a plurality of parts. A gap region for making a drain current flow therethrough exists between adjacent ones of the divided parts of the buried region.
Another method according to the present invention is a method for fabricating a semiconductor device including: a semiconductor layer of a first conductivity type; a source region of a second conductivity type, the source region being formed within the semiconductor layer; a drain region of the second conductivity type, the drain region being formed within the semiconductor layer; a channel region provided between the source and drain regions; a gate electrode formed over the channel region; and a buried region of the first conductivity type, at least part of the buried region being included in the drain region. The method includes the steps of: doping the semiconductor layer with a dopant of the second conductivity type for the drain region; and doping the semiconductor layer with a dopant of the first conductivity type for the buried region, thereby forming the buried region divided into a plurality of parts.